1. Field of the Invention
This invention relates generally to the field of memory systems, and more particularly, to controlling multiple memory channels.
2. Description of the Related Art
With present-day computer systems becoming increasingly more complex, and advances in technology leading to ever increasing processor speeds, it is becoming more and more difficult to optimize system performance, which oftentimes depends largely on the bandwidth and latency of the given system's memory. Consequently, accessing memory with the lowest latency, and highest use of memory bandwidth may improve and/or optimize the system's performance. As the required time to access the memory and complete a given memory request increases, the system slows down. Thus, any reduction in access time, and/or an overall increase in throughput on the memory bus may benefit system performance.
A large number of systems, including desktop computers, graphics adapter cards and notebook computers among others, use Dynamic random access memory (DRAM). DRAM devices provide many advantages over other memory technologies, including and most notably, static random access memory (SRAM) devices. The most important of these benefits are higher storage densities and less power consumption. However, these benefits come at the expense of various time delays incurred when preparing the memory cells and other components within DRAM devices for each subsequent access, for example before/after each read/write access. Examples of such delays include the time required to perform row precharge, row refresh, and row activation. In order to more precisely manage and control memory operations when incurring these delays, additional commands—which are transmitted between read/write accesses—have been created, resulting in additional overhead. In order to improve system performance and design by making memory management transparent to central processing units, memory access is typically managed by dedicated memory controllers, which control the flow of data to/from the memory and execute necessary memory management commands such as row precharge and row activate.
A large percentage of DRAMs in use today belong to the double-data-rate synchronous DRAM (DDR SDRAM) family. DDR SDRAM (including DDR2 and DDR3) achieves greater bandwidth than single-data-rate SDRAM by transferring data on the rising and falling edges of a strobe signal based on the system the clock. This effectively doubles the transfer rate, thereby improving system performance, without requiring an increase in the frequency of the memory bus. In addition to data transfer speed, the performance of a system will also be affected by the memory bus width. In general, the bus width is determined by how many parallel data lines are available to communicate with the memory cells. A memory controller's bus width will also determine how many bits of data the controller can manage at a time. This can range anywhere from 8 bits in earlier systems, to 256 bits in more complicated systems and graphics cards. To further increase DRAM performance, in this case by addressing the bus width, many motherboards are configured with dual-channel memory, doubling the data throughput between the DRAM and the memory controller by effectively doubling the bus width.
Dual-channel (or more generally multi-channel) technology was created to address mainly the issue of bottlenecks. As previously indicated, the configuration of a memory controller will typically determine the type and speed of DRAM that can be used, as well as the maximum size of each individual memory module, and overall memory capacity of the system. Memory controllers exist with a variety of built-in features and capabilities, but in the past they were typically configured to provide control for a single memory channel. Advantages of single-channel memory controllers include its low cost and flexibility. However, single-channel memory controllers may create a bottleneck when their performance is not sufficient to track the performance of the CPU. In many cases, the CPU may remain idle, absent of data to process if the memory controller is unable to maintain the required data flow. As a general rule, most single-channel memories experience this bottleneck effect when the CPU bus throughput exceeds the bus throughput of the single memory channel.
A dual-channel configuration typically alleviates this bottleneck problem by effectively doubling the amount of available memory bandwidth. Instead of a single memory channel, a second parallel channel is added to reduce the bottleneck by operating two memory channels simultaneously. Thus, dual-channel architecture may make use of existing SDRAM (e.g. DDR) technology and improve the method(s) by which memory is accessed. To use dual-channel memory controllers, the DRAM devices are typically separated onto two different buses to allow two memory controllers to access them in parallel, thus doubling the theoretical amount of bandwidth of the bus. From a functional perspective, more channels could be built (a channel for every DRAM cell might prove to be an ideal solution), but due to wire count, line capacitance, and the need for identical lengths for parallel access lines, additional channels are generally very difficult to implement. Presently, higher end graphics subsystems may be implemented with four, 64-bit simultaneous memory controllers operating in parallel, to manage a total of 256 lines of data at a time. In some cases, memory controllers that support multiple channels may be designed to operate in “ganged mode”, where, for example, two 64-bit memory controllers can be used to access a 128-bit memory device, or manage a single logical 128-bit interface.
Many computing architectures that require high reliability memory subsystems use redundant memory devices and an error correcting code, (ECC) to correct potential errors that might occur during operation. The ECC can oftentimes be configured with a multi-bit symbol to correct errors that result from an inoperative memory device. This configuration/use of ECC is often referred to as “chip kill ECC”. Dual-channel configurations are relevant to chip kill ECC. In fact, chip kill ECC may be one reason why memory controllers that support multiple channels may be configured to operate in ganged mode, if the bandwidth required by the chip kill ECC was greater than the data path width of the memory devices. For example, support for x4 chip kill ECC would mean that any 4-bit symbol should be fixable, even if it is completely bad. The number of x4 symbols used by the chip kill ECC would determine the size of the required interface, i.e. the required width of the data path. For example, if 32×4 symbols were used, a 128-bit interface would be required.
While overall system performance can be substantially improved by providing support for dual-channel memory, the design complexity and size of memory controllers capable of handling dual-channel configurations become unavoidably greater than that of memory controllers which only provide support for a single channel, especially when dual-channel support is required in both “ganged” and “unganged” configurations. It is thus a challenge to design and build memory controllers capable of dual-channel memory control while remaining area efficient and not much more complex than memory controllers configured for handling only a single memory channel.
Other corresponding issues related to the prior art will become apparent to one skilled in the art after comparing such prior art with the present invention as described herein.